1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices, more particularly, relates to a nonvolatile semiconductor memory device having a memory cell array in which a plurality of memory cells are disposed in the form of a matrix and are divided into a plurality of sectors.
2. Description of the Background Art
A conventional nonvolatile semiconductor memory device such as a flash EEPROM realizes program/erase and read operations using various high voltages. In order to generate these high voltages, a voltage boost circuit for boosting a power supply voltage and outputting a high voltage is generally used. Thus, a nonvolatile semiconductor memory device having a built-in voltage boost circuit is widely used (for example, see Japanese Laid-Open Patent Publication No. 5-290587, pages 4–5, FIG. 1).
Hereinafter, a conventional nonvolatile semiconductor memory device as shown in FIG. 16 will be described. FIG. 16 is a block diagram showing a structure of a conventional EEPROM. A memory cell array 1 is divided into N (N is natural number) sectors S1 to SN. The sectors S1 to SN are electrically rewritable nonvolatile memory cells, and floating gate memory cells MC are arranged and connected in a NOR array configuration as shown in FIG. 17. The drain of each memory cell MC is connected to a bit line BL, the source thereof is connected to a common source line SL, and a control gate thereof is connected to a word line WL. The word line WL of each of the sectors S1 to SN is selected by a row decoder 2 that is divided into N (N is natural number) decoder blocks XDEC1 to XDECN, and the bit line BL is selected by a column gate 4 that is driven by a column decoder 3. An address AD is inputted to an address/data buffer 5, and a row address and a column address are decoded by the row decoder 2 and the column decoder 3, respectively.
When data is read, bit line data selected by the column gate 4 is detected and amplified by a sense amplifier 6, and outputted from an I/O terminal via the address/data buffer 5. Also, when data is written, data DB inputted from the I/O terminal is latched by the sense amplifier 6 via the address/data buffer 5, and the latched data DB is transferred to the bit line BL selected by the column gate 4.
The high-voltage generation boost circuit 7 and the low-voltage generation boost circuit 8 are provided for generating a boost voltage higher than a power supply voltage that is necessary to program/erase/read data. A low boost output voltage VPPL of the low-voltage generation boost circuit 8 is supplied to a regulator circuit 9. After the voltage is stabilized, the regulator circuit 9 outputs a regulator output voltage VRO. Also, a high boost output voltage VPPH of the high-voltage generation boost circuit 7 is supplied to a voltage changing switch circuit 10 along with the regulator output voltage VRO of the regulator circuit 9. In accordance with a switch control signal supplied from a control circuit 11, the voltage changing switch circuit 10 selects the high boost output voltage VPPH or the regulator output voltage VRO of the regulator circuit 9, and supplies the selected voltage to the row decoder 2 as word line supply voltages Vwll to VwlN. In accordance with to a mode signal MD, a chip enable signal CEB, a program enable signal WEB, and an output enable signal OEB, the control circuit 11 controls the address/data buffer 5, the high-voltage generation boost circuit 7, the low-voltage generation boost circuit 8, the regulator circuit 9, and the voltage changing switch circuit 10 so that each circuit performs a predetermined operation according to a data program/erase/read mode.
FIG. 18 shows one example of the high-voltage generation boost circuit 7. In FIG. 18, a two-phase clock voltage boost circuit driven by a boost clock is shown. In this two-phase clock voltage boost circuit, diode-connected NMOS transistors Mn1 to Mn6, and Mn10 are connected in series to form a seven-stage circuit. An input terminal of the first NMOS transistor Mn1 is fixed to a power supply potential Vcc (=2.5V), smoothing capacitance Co and a Zener diode Dzh are inserted between an output terminal, which supplies the high boost output voltage VPPH, and a ground potential Vss, and a switch circuit 12 that is electrically connected/disconnected in accordance with a stop mode signal is inserted between the output terminal and the power supply potential Vcc.
FIG. 19 shows one example of the low-voltage generation boost circuit 8. In FIG. 19, any component elements that have similar counterparts in FIG. 18 are denoted by the same reference numerals as those used therein. In FIG. 19, diode-connected NMOS transistors Mn1 to Mn4, and Mn10 are connected in series to form a five-stage circuit, and a Zener diode Dzl is inserted between an output terminal, which supplies the low boost output voltage VPPL, and the ground potential Vss.
As shown in FIG. 20, the regulator circuit 9 includes a comparator CMP, which uses the low boost output voltage VPPL as a power supply, and a PMOS transistor Mp1 that is controlled to turn ON/OFF by an output of the comparator CMP and is connected in series between a VPPL node and a VSS terminal. In this case, the drain terminal of the PMOS transistor Mp1 functions as an output terminal, and supplies the regulator output voltage VRO. A VRO output terminal is provided with a resistance voltage divider circuit, in which resistances R1 to R3 are connected in series, and a feedback voltage VFB of the resistance R3 is fed back to a noninverting input terminal of the comparator CMP. A reference voltage VREF is inputted to an inverting input terminal of the comparator CMP. Therefore, ON/OFF control of the PMOS transistor Mp1 is performed so that a feedback voltage VFB is equal to the reference voltage VREF. Also, a short-circuit PMOS transistor Mp2, which is controlled by a mode control signal RDB, is connected between a node NR, which exists between the resistances R1 and R2, and the VRO output terminal. For example, a potential is controlled so that a mode control signal RDB is deactivated and the PMOS transistor Mp2 is turned ON in a read operation, whereas the PMOS transistor Mp2 is turned OFF in a program verify operation. As a result, for example, it is possible to output a VRO of 4.5V in a read operation, and output a VRO of 5.5V in a program verify operation. Also, a switch circuit 13, which is controlled by a stop mode signal, is inserted between the VRO output terminal and a Vcc power supply terminal, and a switch circuit 14, which is controlled by a stop mode bar signal, is provided between a node N1 of the resistance R3 and a Vss ground terminal.
FIG. 21 shows one example of a unit decoder comprising the row decoder 2. The unit decoder consists of a NAND gate G1 carrying out the logical product (AND) between a plurality of row addresses ADR, a level shift circuit 15, and a driver circuit 16. In a unit decoder selected from among the N decoder blocks, a node N2 is deactivated. The level shift circuit 15 consists of PMOS transistors Mp3 and Mp4, NMOS transistors Mn11 and Mn12, and an inverter gate G2. A signal of the node N2 is inputted to a gate of the NMOS transistor Mn11, and an inversion signal of the node N2 is inputted to a gate of the NMOS transistor Mn12. The driver circuit 16 is an inverter circuit consisting of an NMOS transistor Mn13 and a PMOS transistor Mp5. The driver circuit 16 uses an output of the level shift circuit 15 as an input, and uses a word line supply voltage Vwll as a power supply. An output voltage of the driver circuit 16 is applied to the control gate of the memory cell MC. Also, in this case, all N-well nodes NW of the PMOS transistors Mp3 to Mp5 are connected to the word line supply voltage Vwll.
Hereinafter, an operation of the above-described nonvolatile semiconductor memory device will be described. In a data program operation, the high boost output voltage VPPH (=10V) is applied, as a word line WL voltage, to the control gate of the memory cell MC that is selected in accordance with a program address AD and a data DB input, and 0V is applied to a non-selected word line WL. At this time, in accordance with the data DB to be written, 5V or 0V is applied to the bitline BL. Also, 0V is applied to the common source line SL. As a result, writing is performed on the memory cell MC that is connected to a selected word line WL and whose drain terminal is provided with 5V via the bit line BL, an electron is added to the floating gate, and a threshold value of the memory cell MC increases in a normal direction.
Specific operations of the power supply circuit and the decoder 2 are as follows: A boost clock is inputted to the high-voltage generation boost circuit 7 as shown in FIG. 18 from the control circuit 11. A boost voltage higher than a power supply voltage is generated by a known charge transfer operation, and clamped to 10V by the Zener diode Dzh provided on the output terminal, and the high boost output voltage VPPH (=10V) is supplied to the voltage changing switch circuit 10. At this time, a stop mode signal inputted from the control circuit 11 is deactivated, and the switch circuit 12 is electrically disconnected. Also, a boost clock is inputted to the low-voltage generation boost circuit 8 as shown in FIG. 19 in a similar manner. A boost voltage higher than a power supply voltage is generated and clamped to 7V by the Zener diode Dzl provided on the output terminal, and the low boost output voltage VPPL (=7V) is supplied to the regulator circuit 9. At this time, a stop mode signal is activated and a stop mode bar signal is deactivated since the regulator circuit 9 as shown in FIG. 20 stops during a program operation. As a result, the switch circuit 13 is electrically connected, whereas the switch circuit 14 is electrically disconnected, and the regulator output voltage VRO (=Vcc) is supplied to the voltage changing switch circuit 10.
In the voltage changing switch circuit 10, the high boost output voltage VPPH (=10V) is selected in accordance with a switch control signal supplied from the control circuit 11, and supplied to all the decoder blocks XDEC1 to XDECN of the row decoder 2 as word line supply voltages Vwll to VwlN. At this time, as shown in FIG. 21, a very large load capacitance such as the N-well node NW, which is used in common by all the decoder blocks XDEC1 to XDECN, is charged by the word line supply voltages Vwll to VwlN. After charge is completed, a predetermined word line WL is selected, and only a node N2 of a unit decoder driving the selected word line WL is deactivated. Thus, the high boost output voltage VPPH (=10V) is outputted and applied to the control gate of the selected memory cell MC. Voltages of non-selected word lines WL are not changed (=0V).
Next, in a program verify operation, 1V is applied to the selected bit line BL at the same time as the regulator output voltage VRO (=5.5V) is applied to a control gate of a cell for which writing is performed. Also, 0V is applied to the common source line. At this time, a bit line potential is detected and amplified by the sense amplifier 6 to determine whether the above cell is a cell for which writing has been performed or a cell for which erasure has been performed. When it is determined that the above cell is a cell for which writing has been performed, a next program operation is cancelled. On the other hand, when it is determined that the above cell is a cell for which erasure has been performed, a next program operation is performed. Specific circuit operations of the power supply circuit and the row decoder 2 are as follows: a stop mode signal is activated at the same time as a boost clock to be supplied to the high-voltage generation boost circuit 7 as shown in FIG. 18 is stopped, and the switch circuit 12 is electrically connected. As a result, a power supply potential Vcc is supplied to the voltage changing switch circuit 10.
As is the case with the program operation, a boost clock is inputted to the low-voltage generation boost circuit 8 as shown in FIG. 19. A boost voltage higher than a power supply voltage is generated and clamped to 7V by the Zener diode Dzl provided on the output terminal, and the low boost output voltage VPPL (=7V) is supplied to the regulator circuit 9. At this time, in the regulator circuit 9 as shown in FIG. 20, a mode control signal RDB is activated, the PMOS transistor Mp2 is OFF, and the resistance R1 is enabled. At the same time, a stop mode signal is deactivated and as top mode bar signal is activated, whereby the switch circuits 13 and 14 are electrically disconnected and connected, respectively. As a result, the regulator output voltage VRO (=5.5V) is supplied to the voltage changing switch circuit 10.
Next, in the voltage changing switch circuit 10, the regulator output voltage VRO (=5.5V) is selected in accordance with a switch control signal supplied from the control circuit 11, and supplied to all the decoder blocks XDEC1 to XDECN of the row decoder 2 as word line supply voltages Vwll to VwlN. At this time, as shown in FIG. 21, a load capacitance such as the N-well node NW, which is used in common by all the decoder blocks XDEC1 to XDECN, is charged by the word line supply voltages Vwll to VwlN. After charge is completed, a predetermined word line WL is selected, and the regulator output voltage VRO (=5.5V) is outputted and applied to a control gate of the selected memory cell MC. Voltages of non-selected word lines WL are not changed (=0V).
FIG. 22 shows a timing chart indicating a voltage system supplied to a word line WL during the above-described program/program verify operation. First, in a stop state (STOP), word line supply voltages Vwll to VwlN coincide with a power supply potential Vcc due to a stopped state of the high-voltage generation boost circuit 7, the low-voltage generation boost circuit 8, and the regulator circuit 9. Next, when a transition is made to a program state (Program), the high-voltage generation boost circuit 7 and the low-voltage generation boost circuit 8 enter an operation state. In this state, the high-voltage generation boost circuit 7 charges a load capacitance from the power supply potential Vcc up to a high boost output voltage VPPH (=10V), and the low-voltage generation boost circuit 8 charges a load capacitance from the power supply potential Vcc up to a low boost output voltage VPPL (=7V). At this time, the voltage changing switch circuit 10 causes the high boost output voltage VPPH (=10V) to pass through the row decoder 2, whereby a load capacitance seen by the high-voltage generation boost circuit 7 becomes very large. As a result, it is necessary to take a very long setup time 11.
Next, when a transition is made from a program state to a program verify state (PV), the high-voltage generation boost circuit 7 enters a stopped state, and the high boost output voltage VPPH (=10V) is discharged to a power supply potential Vcc. Also, the regulator circuit 9 is in an operation state, and the regulator output voltage VRO (=5.5V) obtained by stepping down the low boost output voltage VPPL (=7V) is supplied to the row decoder 2 via the voltage changing switch circuit 10. In the case where it is not determined that writing is completed in the above PV operation, a transition is made to next Program and PV operations. Note that a load capacitance is charged from the regulator output voltage VRO (=5.5V) . Thus, a setup time τ l to reach the high boost output voltage VPPH (=10V) in a second or later program mode is slightly shorter than the first setup time τ l1. Hereinafter, the above-described program/program verify operation is repeated until writing is performed for all desired memory cells MC.
As described above, in a method in which a program/program verify operation is repeated, if necessary, a plurality of times, a very large load capacitance such as the N-well node NW of the row decoder 2 has to be charged by the high boost output voltage VPPH (=10V) every time a transition is made to a program mode. As a result, it is necessary to take a very long setup time τ l every time a loop is executed. Thus, the conventional nonvolatile semiconductor memory device has disadvantages in that power consumption of the high-voltage generation boost circuit 7 which supplies a high boost charge is increased due to a very long time required for a program/program verify operation and a very large load capacitance to be charged and discharged by a high boost charge. Also, another disadvantage is that power consumption is increased if current supply capacity of the high-voltage generation boost circuit 7 generating VPPH is enhanced in order to reduce τ l.
As such, the above-described structure has disadvantages in that it is difficult to reduce a time required for a program/program verify operation and power consumption, and that power consumption is increased by reducing a time required for a program/program verify operation.